 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Micrel, Inc. 3.3V 32-175Mbps AnyRate(R) CLOCK AND DATA RECOVERY SY87700L SY87700L FEATURES Industrial temperature range (-40C to +85C) 3.3V power supply SONET/SDH/ATM compatible Clock and data recovery from 32Mbps up to 175Mbps NRZ data stream, clock generation from 32Mbps to 175Mbps Two on-chip PLLs: one for clock generation and another for clock recovery Selectable reference frequencies Differential PECL high-speed serial I/O Line receiver input: no external buffering needed Link Fault indication 100k ECL compatible I/O Complies with Bellcore, ITU/CCITT and ANSI specifications for applications such as OC-1 and OC-3 as well as proprietary applications Available in 32-pin EPAD-TQFP and 28-pin SOIC packages (28-pin SOIC is available, but is not recommended for new designs.) DESCRIPTION The SY87700L is a complete Clock Recovery and Data Retiming integrated circuit for data rates from 32Mbps up to 175Mbps NRZ. The device is ideally suited for SONET/SDH/ATM applications and other high-speed data transmission systems. Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the incoming data stream. The VCO center frequency is controlled by the reference clock frequency and the selected divide ratio. On-chip clock generation is performed through the use of a frequency multiplier PLL with a byte rate source as reference. The SY87700L also includes a link fault detection circuit. All support documentation can be found on Micrel's web site at: www.micrel.com. APPLICATIONS SONET/SDH/ATM OC-1 and OC-3 Fast Ethernet, SMPTE 259 Proprietary architecture up to 175Mbps BLOCK DIAGRAM PLLR P/N RDOUTP (PECL) RDOUTN 0 1 PHASE/ FREQUENCY DETECTOR LINK FAULT DETECTOR RDINP (PECL) RDINN PHASE DETECTOR CHARGE PUMP VCO RCLKP (PECL) RCLKN CD (PECL) REFCLK (TTL) LFIN (TTL) PHASE/ FREQUENCY DETECTOR CHARGE PUMP VCO 1 0 TCLKP (PECL) TCLKN DIVIDER BY 8, 10, 16, 20 SY87700L DIVSEL 1/2 (TTL) PLLS P/N FREQSEL 1/2/3 (TTL) CLKSEL (TTL) VCC VCCA VCCO GND AnyRate is a registered trademark of Micrel, Inc. M9999-111406 hbwhelp@micrel.com or (408) 955-1690 Rev.: H Amendment: /0 1 Issue Date: September 2006 Micrel, Inc. SY87700L PACKAGE/ORDERING INFORMATION Ordering Information(1) VCCA 1 LFIN 2 DIVSEL1 3 RDINP 4 RDINN 5 FREQSEL1 6 REFCLK 7 FREQSEL2 8 FREQSEL3 9 N/C 10 PLLSP 11 PLLSN 12 GND 13 GND 14 28 VCC 27 CD 26 DIVSEL2 25 RDOUTP 24 RDOUTN 23 VCCO 22 RCLKP 21 RCLKN 20 VCCO 19 TCLKP 18 TCLKN 17 CLKSEL 16 PLLRP 15 PLLRN Part Number SY87700LZI SY87700LZITR(2) SY87700LHI SY87700LHITR(2) SY87700LZG(3) SY87700LZGTR(2, 3) SY87700LHG SY87700LHGTR(2, 3) Package Operating Type Range Z28-1 Z28-1 H32-1 H32-1 Z28-1 Z28-1 H32-1 H32-1 Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Package Marking SY87700LZI SY87700LZI SY87700LHI SY87700LHI Lead Finish Sn-Pb Sn-Pb Sn-Pb Sn-Pb SY87700LZG with NiPdAu Pb-Free bar line indicator Pb-Free SY87700LZG with NiPdAu Pb-Free bar line indicator Pb-Free SY87700LHG with NiPdAu Pb-Free bar line indicator Pb-Free SY87700LHG with NiPdAu Pb-Free bar line indicator Pb-Free 28-Pin SOIC (Z28-1) 32 31 30 29 28 27 26 25 NC RDINP RDINN FREQSEL1 REFCLK FREQSEL2 FREQSEL3 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 RDOUTP RDOUTN VCCO RCLKP RCLKN VCCO TCLKP TCLKN 32-Pin EPAD TQFP (H32-1) M9999-111406 hbwhelp@micrel.com or (408) 955-1690 PLLSP PLLSN GNDA GND GND PLLRN PLLRP CLKSEL DIVSEL1 LFIN VCCA VCCA VCC VCC CD DIVSEL2 Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs. 2 Micrel, Inc. SY87700L PIN DESCRIPTIONS Pin Number SOIC 4 5 Pin Number TQFP 2 3 Pin Name RDINP, RDINN Pin Function Serial Data Input (Differential PECL): These built-in line receiver inputs are connected to the differential receive serial data stream. An internal receive PLL recovers the embedded clock (RCLK) and data (RDOUT) information. The incoming data rate can be within one of five frequency ranges depending on the state of the FREQSEL pins. See "Frequency Selection" table. Reference Clock (TTL Inputs): This input is used as the reference for the internal frequency synthesizer and the "training" frequency for the receiver PLL to keep it centered in the absence of data coming in on the RDIN inputs. Carrier Detect (PECL Input): This input controls the recovery function of the Receive PLL and can be driven by the carrier detect output of optical modules or from external transition detection circuitry. When this input is HIGH the input data stream (RDIN) is recovered normally by the Receive PLL. When this input is LOW the data on the inputs RDIN will be internally forced to a constant LOW, the data outputs RDOUT will remain LOW, the Link Fault Indicator output LFIN forced LOW and the clock recovery PLL forced to look onto the clock frequency generated from REFCLK. Frequency Select (TTL Inputs): These inputs select the output clock frequency range as shown in the "Frequency Selection" table. Divider Select (TTL Inputs): These inputs select the ratio between the output clock frequency (RCLK/TCLK) and the REFCLK input frequency as shown in the "Reference Frequency Selection" table. Clock Select (TTL Inputs): This input is used to select either the recovered clock of the receiver PLL (CLKSEL = HIGH) or the clock of the frequency synthesizer (CLKSEL = LOW) to the TCLK outputs. Link Fault Indicator (TTL Output): This output indicates the status of the input data stream RDIN. Active HIGH signal is indicating when the internal clock recovery PLL has locked onto the incoming data stream. LFIN will go HIGH if CD is HIGH and RDIN is within the frequency range of the Receive PLL (1000ppm). LFIN is an asynchronous output. Receive Data Output (Differential PECL): These ECL 100k outputs represent the recovered data from the input data stream (RDIN). This recovered data is specified against the rising edge of RCLK. Clock Output (Differential PECL): These ECL 100k outputs represent the recovered clock used to sample the recovered data (RDOUT). Clock Output (Differential PECL): These ECL 100k outputs represent either the recovered clock (CLKSEL = HIGH) used to sample the recovered data (RDOUT) or the transmit clock of the frequency synthesizer (CLKSEL = LOW). Clock Synthesis PLL Loop Filter. External loop filter pins for the clock synthesis PLL. Clock Recovery PLL Loop Filter. External loop filter pins for the receiver PLL. Supply Voltage(1) Analog Supply Voltage(1) Output Supply Voltage(1) Ground No Connect 7 5 REFCLK 27 26 CD 6 8 9 3 26 17 4 6 7 32 25 16 FREQSEL1, FREQSEL2, FREQSEL3 DIVSEL1, DIVSEL2 CLKSEL 2 31 LFIN 25 24 22 21 19 18 24 23 21 20 18 17 RDOUTP, RDOUTN RCLKP, RCLKN TCLKP, TCLKN 11 12 16 15 1 20, 23 13, 14 10 9 10 15 14 27, 28, 29, 30 19, 22 12, 13 1, 8 PLLSP, PLLSN PLLRP, PLLRN VCC VCCA VCCO GND NC Note: 1. VCC, VCCA, VCCO must be the same value. M9999-111406 hbwhelp@micrel.com or (408) 955-1690 3 Micrel, Inc. SY87700L FUNCTIONAL DESCRIPTION Clock Recovery Clock Recovery, as shown in the block diagram generates a clock that is at the same frequency as the incoming data bit rate at the Serial Data input. The clock is phase aligned by a PLL so that it samples the data in the center of the data eye pattern. The phase relationship between the edge transitions of the data and those of the generated clock are compared by a phase/frequency detector. Output pulses from the detector indicate the required direction of phase correction. These pulses are smoothed by an integral loop filter. The output of the loop filter controls the frequency of the Voltage Controlled Oscillator (VCO), which generates the recovered clock. Frequency stability without incoming data is guaranteed by an alternate reference input (REFCLK) that the PLL locks onto when data is lost. If the Frequency of the incoming signal varies by greater than approximately 1000ppm with respect to the synthesizer frequency, the PLL will be declared out of lock, and the PLL will lock to the reference clock. The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the minimum transition density expected in a received SONET data signal. This transfer function yields a 30s data stream of continuous 1's or 0's for random incoming NRZ data. The total loop dynamics of the clock recovery PLL provides jitter tolerance which is better than the specified tolerance in GR-253-CORE. Lock Detect The SY87700L contains a link fault indication circuit which monitors the integrity of the serial data inputs. If the received serial data fails the frequency test, the PLL will be forced to lock to the local reference clock. This will maintain the correct frequency of the recovered clock output under loss of signal or loss of lock conditions. If the recovered clock frequency deviates from the local reference clock frequency by more than approximately 1000ppm, the PLL will be declared out of lock. The lock detect circuit will poll the input data stream in an attempt to reacquire lock to data. If the recovered clock frequency is determined to be within approximately 1000ppm, the PLL will be declared in lock and the lock detect output will go active. M9999-111406 hbwhelp@micrel.com or (408) 955-1690 4 Micrel, Inc. SY87700L CHARACTERISTICS Performance The SY87700L PLL complies with the jitter specifications proposed for SONET/SDH equipment defined by the Bellcore Specifications: GR-253-CORE, Issue 2, December 1995 and ITU-T Recommendations: G.958 document, when used with differential inputs and outputs. Input Jitter Tolerance Input jitter tolerance is defined as the peak-to-peak amplitude of sinusoidal jitter applied on the input signal that causes an equivalent 1dB optical/electrical power penalty. SONET input jitter tolerance requirement condition is the input jitter amplitude which causes an equivalent of 1dB power penalty. A Jitter Transfer Jitter transfer function is defined as the ratio of jitter on the output OC-N/STS-N signal to the jitter applied on the input OC-N/STS-N signal versus frequency. Jitter transfer requirements are shown in Figure 2. Jitter Generation The jitter of the serial clock and serial data outputs shall not exceed .01 U.I. rms when a serial data input with no jitter is presented to the serial data inputs. Jitter Transfer (dB) 0.1 Sinusoidal Input Jitter Amplitude (UI p-p) 15 1.5 -20dB/decade -20dB/decade -20dB/decade -20 Acceptable Range 0.40 f0 f1 f2 Frequency f4 ft fc Frequency OC/STS-N Level 3 f0 (Hz) 10 f1 (Hz) 30 f2 (Hz) 300 f3 (kHz) 6.5 ft (kHz) 65 OC/STS-N Level 3 fc (kHz) 130 P (dB) 0.1 Figure 1. Input Jitter Tolerance Figure 2. Jitter Transfer M9999-111406 hbwhelp@micrel.com or (408) 955-1690 5 Micrel, Inc. SY87700L FREQUENCY SELECTION TABLE FREQSEL1 0 1 1 1 1 0 0 FREQSEL2 1 0 0 1 1 1 0 FREQSEL3 1 0 1 0 1 0 X(2) fVCO/fRCLK 6 8 12 16 24 -- -- fRCLK Data Rates (Mbps) 125 - 175 94 - 157 63 - 104 47 - 78 32 - 52 undefined undefined Notes: 1. SY87700L operates from 32-175MHz. For higher speed applications, the SY87701L operates from 32MHz to 1250MHz. 2. X is a DON'T CARE. REFERENCE FREQUENCY SELECTION DIVSEL1 0 0 1 1 DIVSEL2 0 1 0 1 fRCLK/fREFCLK 8 10 16 20 LOOP FILTER COMPONENTS(1) R5 C3 PLLSP PLLSN Wide Range R5 = 350 C3 = 1.0F (X7R Dielectric) R6 C4 PLLRP PLLRN Wide Range R6 = 680 C4 = 1.0F (X7R Dielectric) Note: 1. Suggested Values. Values may vary for different applications. M9999-111406 hbwhelp@micrel.com or (408) 955-1690 6 Micrel, Inc. SY87700L Absolute Maximum Ratings(1) Supply Voltage (VCC) .................................. -0.5V to +4.0V Input Voltage (VIN) ......................................... -0.5V to VCC Output Current (IOUT) Continuous ............................................................. 50mA Surge .................................................................... 100mA Lead Temperature (soldering, 20 sec.) ..................... 260C Storage Temperature (TS) ....................... -65C to +150C Operating Ratings(2) Supply Voltage (VCC) .............................. +3.15V to +3.45V Ambient Temperature (TA) ......................... -40C to +85C Package Thermal Resistance(3) SOIC (JA)(4) ..................................................................... 80C/W EPAD TQFP (JA)(5) 0lfpm airflow ................................................. 27.6C/W 200lfpm airflow ............................................. 22.6C/W 500lfpm airflow ............................................. 20.7C/W DC ELECTRICAL CHARACTERISTICS Symbol VCC ICC Parameter Power Supply Voltage Power Supply Current Condition Min 3.15 Typ 3.3 170 Max 3.45 230 Units V mA PECL 100K DC ELECTRICAL CHARACTERISTICS VCC = VCCO = VCCA = 3.3V 5%; TA = -40C to +85C; unless noted. Symbol VIH VIL VOH VOL IIL Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Input LOW Current 50 to VCC -2V 50 to VCC -2V VIN = VIL(min) Condition Min VCC -1.165 VCC -1.810 VCC -1.075 VCC -1.860 0.5 Typ -- -- -- -- -- Max VCC -0.880 VCC -1.475 VCC -0.830 VCC -1.570 -- Units V V V V A TTL DC ELECTRICAL CHARACTERISTICS VCC = VCCO = VCCA = 3.3V 5%; TA = -40C to +85C; unless noted. Symbol VIH VIL VOH VOL IIH IIL IOS Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input LOW Current Output Short Circuit Current IOH = -0.4mA IOL = 4mA VIN = 2.7V, VCC = max. VIN = VCC, VCC = max. VIN = 0.5V, VCC = max. VOUT = 0V (maximum 1 sec) Condition Min 2.0 -- 2.0 -- -125 -- -300 -15 Typ -- -- -- -- -- -- -- -- Max VCC 0.8 -- 0.5 -- +100 -- -100 Units V V V V A A A mA Notes: 1. Permanent device damage may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to "Absolute Maximum Ratings" conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Airflow of 500lfpm recommended for 28-pin SOIC. 4. 28-pin SOIC package is NOT recommended for new designs. 5. Using JEDEC standard test boards with die attach pad soldered to PCB. See www.amkor.com for additional package details. M9999-111406 hbwhelp@micrel.com or (408) 955-1690 7 Micrel, Inc. SY87700L AC ELECTRICAL CHARACTERISTICS VCC = VCCO = VCCA = 3.3V 5%; TA = -40C to +85C; unless noted. Symbol fVCO fVCO tACQ tCPWH tCPWL tir tODC tr, tf tSKEW tDV tDH Parameter VCO Center Frequency VCO Center Frequency Tolerance Acquisition Lock Time REFCLK Pulse Width HIGH REFCLK Pulse Width LOW REFCLK Input Rise Time Output Duty Cycle (RCLK/TCLK) ECL Output Rise/Fall Time (20% to 80%) Recovered Clock Skew Data Valid Data Hold 50 to VCC -2V Condition fREFCLK x Byte Rate Nominal Min 750 -- -- 4 4 -- 45 100 -200 1/(2 x fRCLK) - 200 1/(2 x fRCLK) - 200 Typ -- 5 -- -- -- 0.5 -- -- -- -- -- Max 1250 -- 15 -- -- 2 55 500 +200 -- -- Units MHz % s ns ns ns % of UI ps ps ps ps TIMING WAVEFORMS tCPWL tCPWH REFCLK tODC tODC RCLK tSKEW tDV tDH RDOUT M9999-111406 hbwhelp@micrel.com or (408) 955-1690 8 Micrel, Inc. SY87700L 32-PIN APPLICATION EXAMPLE VCC R13 LED D2 Q1 2N2222A R12 DIVSEL1 DIVSEL2 VCCA VCCA LFIN VCC VCC VEE DIODE D1 CD 32 31 30 29 28 27 26 25 RDOUTP RDOUTN VCCO RCLKP RCLKN VCCO TCLKP TCLKN VCC 1N4148 R3 R4 R5 R6 R7 R8 R9 R10 NC RDINP RDINN FREQSEL1 REFCLK FREQSEL2 CLKSEL DIVSEL1 DIVSEL2 CD FREQSEL3 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 PLLRN PLLSP PLLSN VEEA VEE VEE PLLRP CLKSEL VEE R11 1k SW1 C3 C4 GND Ferrite Bead BLM21A102 R1 C1 C2 R2 VCC VCCO (+2V) VCC (+2V) VCCA (+2V) L3 L2 C5 22F L1 C6 0.1F C7 6.8F C8 6.8F C11 0.1F C13 0.1F C9 6.8F C15 0.1F C12 0.01F C14 0.01F C16 0.01F GND C10 6.8F C17 0.1F C18 0.01F VEE (-1.3V) VEE C19 1.0F C20 0.1F C21 0.01F VEEA (-1.3V) Note: C3, C4 are optional. C1 = C2 = 1.0F R1 = 350 R2 = 680 R3 through R10 = 5k R12 = 12k R13 = 130 M9999-111406 hbwhelp@micrel.com or (408) 955-1690 9 Micrel, Inc. SY87700L 28-PIN APPLICATION EXAMPLE GND SW1 VCC 1 2 3 4 5 6 (R17 - R22) 5k x 6 R8 130 LED D2 Ferrite Bead BLM21A102 VCC Stand Off 0.1F FB1 C9 22F 0.1F C8 C7 22F C6 GND Capacitor Pads (1206 format) R1 C1 1 VCC R2 VCCA VCC 28 CD 27 DIVSEL2 26 RDOUTP 25 RDOUTN 24 VCCO 23 RCLKP 22 RCLKN 21 VCCO 20 TCLKP 19 TCLKN 18 CLKSEL 17 R6 R7 1k J1 VCC 0.1F 0.1F C14 C15 2 LFIN 3 DIVSEL1 4 RDINP 5 RDINN Diode D1 1N4148 RDIN C2 R3 R4 6 FREQSEL1 7 REFCLK 8 FREQSEL2 9 FREQSEL3 10 N/C 80 R5 See Table 1 GND 0.1F 0.1F C16 C17 0.1F 0.1F C18 C19 LOOP FILTER NETWORK 11 PLLSP 12 PLLSN 13 GND 14 GND C3 1.5F 50 C4 PLLRP 16 1.0F R11 R12 R13 R14 R15 R16 PLLRN 15 If VCC = +3.3V: R9 through R14 = 220 VCC C5 REFCLK (TTL) NC DPDT Slide Switch GND XTAL Oscillator 14 0.1F C13 Pin 1 (VCCA) 0.1F Pin 28 (VCC) 0.1F Pin 23 (VCCO) 0.1F Pin 20 (VCCO) 0.1F C10 1 C11 VCC 120 R21 8 7 C12 For AC-Coupling Only C1 = C2 = 0.1F R1 = R2 = 680 R3 = R4 = 1k For DC Mode Only C1 = C2 = Shorted R1 = R2 = 130 R3 = R4 = 82 M9999-111406 hbwhelp@micrel.com or (408) 955-1690 10 Micrel, Inc. SY87700L BILL OF MATERIALS (32-PIN EPAD-TQFP) Item C1, C2 C3, C4 C5 C6 C7, C8, C9, C10 C19 C11, C13 C15, C17 C20 C12, C14 C16, C18 C21 D1 D2 J1, J2, J3, J4, J5 J6, J7, J8, J9, J10, J11, J12 L1, L2, L3 Q1 R1 R2 R3, R4, R5, R6 R7, R8, R9, R10 R11 R12 R13 SW1 206-7 CTS Part Number VJ0603Y105JXJAT VJ0603Y105JXJAT ECS-T1ED226R ECU-V1H104KBW ECS-T1EC685R ECJ-3YB1E105K ECU-V1H104KBW ECU-V1H104KBW ECU-V1H104KBW ECU-V1H103KBW ECU-V1H103KBW ECU-V1H103KBW 1N4148 P300-ND/P301-ND 142-0701-851 Panasonic Johnson Components Murata NTE Manufacturer Vishay Vishay Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Description 1.0F Ceramic Capacitor, Size 0603 X7R Dielectric, Loop Filter, Critical 1.0F Ceramic Capacitor, Size 0603 X7R Dielectric, Loop Filter, Optional 22F Tantalum Electrolytic Capacitor, Size D 0.1F Ceramic Capacitor, Size 1206 X7R Dielectric, Power Supply Decoupling 6.8F Tantalum Electrolytic Capacitor, Size C 1.0F Ceramic Capacitor, Size 1206 X7R Dielectric, VEEA Decoupling 0.1F Ceramic Capacitor, Size 1206 X7R Dielectric, VCCO/VCC Decoupling 0.1F Ceramic Capacitor, Size 1206 X7R Dielectric, VCCA/VEEA Decoupling 0.1F Ceramic Capacitor, Size 1206 X7R Dielectric, VEEA Decoupling 0.01F Ceramic Capacitor, Size 1206 X7R Dielectric, VCCO/VCC Decoupling 0.01F Ceramic Capacitor, Size 1206 X7R Dielectric, VCCA/VEEA Decoupling 0.01F Ceramic Capacitor, Size 1206 X7R Dielectric, VEEA Decoupling Diode T-1 3/4 Red LED Gold Plated, Jack, SMA, PCB Mount Qty 2 2 1 1 4 1 1 1 1 1 1 1 1 1 12 BLM21A102F NTE123A Ferrite Beads, Power Noise Suppression 2N2222A Buffer/Driver Transistor, NPN 350 Resistor, 2%, Size 0402 Loop Filter Component, Critical 680 Resistor, 2%, Size 0402 Loop Filter Component, Critical 5k Pull-up Resistors, 2%, Size 1206 1k Pull-down Resistor, 2%, Size 1206 12k Resistor, 2%, Size 1206 130 Pull-up Resistor, 2%, Size 1206 SPST, Gold Finish, Sealed Dip Switch 3 1 1 1 8 1 1 1 1 M9999-111406 hbwhelp@micrel.com or (408) 955-1690 11 Micrel, Inc. SY87700L 28 LEAD SOIC .300" WIDE (Z28-1) Rev. 02 Note: The 28 Lead SOIC package is NOT recommended for new designs. M9999-111406 hbwhelp@micrel.com or (408) 955-1690 12 Micrel, Inc. SY87700L 32 LEAD EPAD TQFP (DIE UP) (H32-1) Rev. 01 Package EP- Exposed Pad Die CompSide Island Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane PCB Thermal Consideration for 32-Pin EPAD-TQFP Package M9999-111406 hbwhelp@micrel.com or (408) 955-1690 13 Micrel, Inc. SY87700L APPENDIX A Layout and General Suggestions 1. 2. 3. 4. 5. 6. 7. 8. Establish controlled impedance stripline, microstrip, or co-planar construction techniques. Signal paths should have, approximately, the same width as the device pads. All differential paths are critical timing paths, where skew should be matched to within 10ps. Signal trace impedance should not vary more than 5%. If in doubt, perform TDR analysis of all high-speed signal traces. Maintain compact filter networks as close to filter pins as possible. Provide ground plane relief under filter path to reduce stray capacitance. Be careful of crosstalk coupling into the filter network. Maintain low jitter on the REFCLK input. Isolate the XTAL oscillator from power supply noise by adequately decoupling. Keep XTAL oscillator close to device, and minimize capacitive coupling from adjacent signals. Higher speed operation may require use of fundamental-tone (third-overtone typically have more jitter) crystal based oscillator for optimum performance. Evaluate and compare candidates by measuring TXCLK jitter. All unused outputs must be terminated. To conserve power, unused PECL outputs can be terminated with a 1k resistor to VEE. MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2006 Micrel, Incorporated. M9999-111406 hbwhelp@micrel.com or (408) 955-1690 14 |
Price & Availability of SY87700LHG
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |